Director - Hardware Engineering, AI Infrastructure Systems

Key responsibilities

• Build the Infrastructure Systems engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in-house and 3rd-party resources

• Define the technical roadmap for the division’s board- and system-level server products—PCIe Gen6/CXL accelerator cards, OAM modules and UBB baseboards, and full 1U/2U rack systems, evolving toward rack-scale solutions including networking fabric and storage architecture—aligned with the next-generation system and silicon roadmap.

• Serve as the technical authority across system implementation, including schematics, PCB stack-ups, high-speed signaling (PCIe Gen5/6, CXL, high-speed SerDes), enterprise memory, power delivery and VRM design, SI/PI methodology, and mechanical/thermal integration.

• Own end-to-end execution from concept through design reviews, bring-up, validation, reliability qualification, DFM/DFT/DFR and mass-production readiness, including NPI and ramp with tier-1 CMs and ODMs. Make the build-vs-partner call on each program leading designs in-house where it differentiates, and co-designing with ODM partners where time-to-market or scale demands it.

• Drive datacenter-grade platform engineering: BMC-based management, Redfish/IPMI, UEFI/BIOS firmware, secure boot and root-of-trust, platform firmware resilience, enterprise RAS features, and out-of-band telemetry.

• Lead the thermal and mechanical strategy for high-power accelerator platforms, including air-cooled rack designs and, where appropriate, direct liquid cooling (DLC) and immersion-ready variants.

• Partner with the Embedded AI engineering leadership within AIS to align board and system-level execution across the two product lines, sharing reference designs, validation assets and CM/ODM relationships wherever it accelerates both streams.

• Collaborate with Platform Architecture, product management, silicon, SDK and software teams to refine and realize platform requirements (e.g. memory topology, interconnect, power states, telemetry) so that the server products showcase the accelerator’s capabilities at rack and cluster scale.

• Engage directly with strategic customers, system integrators and ecosystem partners (hyperscalers, sovereign cloud operators, HPC centres, OEMs/ODMs) to shape requirements and win design-ins.

• Define and enforce engineering processes, documentation standards, validation methodologies and quality gates for the new division, mapped to Axelera’s NPD framework.

• Identify and mitigate technical risks, resolve engineering escalations, and drive debugging and root-cause analysis during development, qualification and early production.

• Own the division’s engineering budget, CAPEX, external engineering spend and vendor relationships.

Qualifications

• 15+ years in hardware engineering for complex electronics products, with at least 5 years in senior leadership roles running multidisciplinary teams.

• Proven track record of shipping datacenter- or server-class compute hardware into volume production: accelerator cards, OAM modules, UBB baseboards, GPU/xPU-class server platforms, compute nodes or rack-level systems.

• Deep expertise in high-speed interfaces (PCIe Gen4/5/6, CXL, high-speed SerDes), server memory, high-current power delivery and VRM design, and high-density PCB layout with rigorous SI/PI methodology.

• Experience with BMC-based platform management, Redfish/IPMI, UEFI/BIOS or equivalent firmware stacks, secure boot/root-of-trust, and enterprise RAS features.

• Working knowledge of datacenter thermal and mechanical design: air-cooled 1U/2U chassis, direct liquid cooling and/or immersion-ready platforms, and rack power delivery at 12V, 48V and OCP power-shelf level.

• Familiarity with datacenter and AI infrastructure compliance and with PCIe and OCP standards.

• Experience working with tier-1 CMs/ODMs on server-class products, including DFM, MP transfer, yield ramp and sustaining engineering.

• Hands-on ability to review schematics, layouts, simulation results and lab validation data and to make the call when the team is stuck.

• Strong strategic thinker, excellent communicator, skilled at decision-making in fast-moving environments, comfortable engaging at C-level with customers and partners.

We offer a flexible working arrangement, with options to

• Work from one of our Axelera AI offices (Florence and Milan in Italy, Amsterdam and Eindhoven in the Netherlands, Leuven in Belgium, Paris in France, Zurich in Switzerland, or Bristol in the United Kingdom) if you're already based in the vicinity. 

• Work fully remotely from the US or any European country (incl. the UK) you are already in. 

• Relocate with us and work from Amsterdam or Eindhoven in the Netherlands, or Bologna, Florence or Milan in Italy.