Research Engineer, Chip Design RL

About the role

We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.

You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will:

• Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
• Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape our roadmap.
• Deliver your work into research and production training runs.
• Collaborate with other researchers and engineers across and outside Anthropic.

You may be a good fit if you

• Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
• Are fluent with industry EDA tools and processes.
• Have taped out chips and have experience going from spec to silicon.
• Know how to balance research exploration with engineering implementation.
• Are passionate about AI's potential and committed to developing safe and beneficial systems.

Strong candidates may also have

• Experience with reinforcement learning, evaluations or environments.
• Built tooling or automation around chip design flows.
• Worked on ML accelerators or high-performance compute hardware.
• Familiarity with high-level synthesis or architecture simulators.